W90P710_05 Datasheet, PDF (440/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Smart Card Host Clock Base Register (SCHI_CBR)
REGISTER
SCHI_CBR0
SCHI_CBR1
ADDRESS
0xFFF8_5010
0xFFF8_5810
R/W
R/W
R/W
DESCRIPTION
Clock base Register 0
Clock base Register 1
31
30
29
28
27
26
RESERVED
23
22
21
20
19
18
RESERVED
15
14
13
12
11
10
RESERVED
7
6
5
4
3
2
8-bit clock base Data
RESET VALUE
0x0000_000C
0x0000_00OC
25
24
17
16
9
8
1
0
BITS
[31:8]
RESERVED
[7:0]
CBR
DESCRIPTIONS
-
Clock Base value.
It specifies number of internal sampling clock pulses for a data bit.
Default to be 0Ch.
This register combining with BLH and BLL (baud rate latches)
determine internal sampling clock frequency. For example, CBR
defaults to be 0Ch and BLH, BLL default to be 1Fh which mean
SCCLK clock frequency is 372 (12 x 31) times of internal sampling
clock frequency. The default values of CBR, BLH and BLL are
corresponding to default values of transmission factors F and D
specified in ISO/IEC 7816-3. The value of 0Ch of CBR means
there're 12 sampling clock pulses to detect a 1-etu (elementary
time unit) data bit on SCIO signal. It is recommended that user
sets CBR to be around 16 to maintain better data integrity and
transmission stability.
Smart Card Host Status Register (SCHI_SCSR)
REGISTER
SCHI_SCSR0
SCHI_SCSR1
ADDRESS
0xFFF8_5014
0xFFF8_5814
R/W
DESCRIPTION
R Smart card Status Register 0
R Smart card Status Register 1
RESET VALUE
0x0000_0060
0x0000_0060
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