W90P710_05 Datasheet, PDF (314/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[2]
[1]
[0]
AC_W_RES
AC_C_RES
Reserved
DESCRIPTIONS
AC-link warm reset control bit, when this bit is set to 1, (AC-link
begin warn reset procedure, after warn reset procedure finished,
this bit will be cleared automatically) the interface signal
AC_SYNC is high, when this bit is set to 0, the interface signal
AC_SYNC is controlled by AC_BCLK input when this bit is set to
1. Note the AC-link spec. shows it need at least 10 us high
duration of AC_SYNC to warn reset AC97.
AC_W_RES=0, AC_SYNC pin is controlled by AC_BCLK input pin
AC_W_RES=1, AC_SYNC pin is forced to high
The AC_W_RES bit is read/write
AC-link cold reset control bit, when this bit is set to 1, the interface
signal AC_RESETB is low, when this bit is set to 0, the signal
AC_RESETB is high. Note the AC-link spec. shows it need at
least 10 us low duration of AC_RESETB to cold reset AC97.
AC_C_RES=0, AC_RESETB pin is set to 1
AC_C_RES=1, AC_RESETB pin is set to 0
The AC_C_RES bit is read/write
-
AC-link output slot 0 (ACTL_ACOS0)
REGISTER
ACTL_ACOS0
ADDRESS R/W
DESCRIPTION
0xFFF0_9030 R/W AC-link out slot 0
RESET VALUE
0x0000_0000
The ACTL_ACOS0 register store the slot 0 value to be shift out by AC-link. Note that write data to
ACTL_ACOS0 register when AC_W_FINISH bit (ACTL_ACCON[3]) is set is invalid. Therefore, check
AC_W_FINISH bit status before write data into ACTL_ACOS0 register.
31
30
29
23
22
21
15
14
13
7
6
5
Reserved
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
VALID_
FRAME
26
25
24
18
17
16
10
9
8
2
1
0
SLOT_VALID[3:0]
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