W90P710_05 Datasheet, PDF (35/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
7.2 System Manager
7.2.1 Overview
The W90P710 System Manager has the following functions.
y System memory map
y Data bus connection with external memory
y Product identifier register
y Bus arbitration
y PLL module
y Clock select and power saving control register
y Power-On setting
7.2.2 System Memory Map
W90P710 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the On-
Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space: 0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space:
0x8000_0000~0xFFDF_FFFF).
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. Please note that when setting the bank control registers, the address
boundaries of consecutive banks must not overlap.
Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access requested to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 16M bytes (by word
format), and 64M bytes on each SDRAM bank.
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Publication Release Date: January 17, 2005
Revision A.2