W90P710_05 Datasheet, PDF (291/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[31:27]
Reserved
[26:17] PCD
[16]
[15:9]
[8]
BCD
Reserved
PLLRDY
[7:1]
LCDPRESC
[0]
CLKSEL
DESCRIPTIONS
Reserved
The ten-bit PCD field is used to derive the LCD panel clock
frequency VCLK from LCD controller clock:
VCLK=(LCD controller clock)/(PCD+2)
Bypass pixel clock divider.
Reserved
Indicate LCDC that PLL is ready, can switch pixel clock source to
PLL clock
These bits pre-scale counter the LCD controller clock
Scale_CLK = PLL_FIN / ( 2*( LCDPRESC + 1 ) )
This bit driver the LCD controller clock source.
0 = external PLL clock 1 = AHB Bus clock
LCD Timing Controller Register 5 (LCDTCON5)
REGISTER
ADDRESS
R/W
DESCRIPTION
LCDTCON5 0xFFF0_80C0 R/W LCD Timing Control Register 5
RESET VALUE
0x0000_0000
31
30
29
23
22
21
Reserved
15
14
13
7
6
5
Reserved
28
27
Reserved
20
19
12
11
Reserved
4
3
MMODE INVVCLK
26
18
ACBF
10
2
INVHSYN
25
17
9
1
INVVSYN
24
16
8
0
INVVDEN
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Publication Release Date: January 17, 2005
Revision A.2