W90P710_05 Datasheet, PDF (516/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Audio Control Register Map, continued
REGISTER
ADDRESS R/W
DESCRIPTION
ACTL_ACOS0
0xFFF0_9030 R/W AC-link out slot 0
ACTL_ACOS1
0xFFF0_9034 R/W AC-link out slot 1
ACTL_ACOS2
0xFFF0_9038 R/W AC-link out slot 2
ACTL_ACIS0
0xFFF0_903
C
R AC-link in slot 0
ACTL_ACIS1
0xFFF0_9040 R AC-link in slot 1
ACTL_ACIS2
0xFFF0_9044 R AC-link in slot 2
Cache Controller Test Registers Map
REGISTER ADDRESS R/W
CTEST0 ^0xFFF6_0000 R/W
DESCRIPTION
Cache test register 0
CTEST1 0xFFF6_0004 R Cache test register 1
UART0 Control Registers Map
REGISTER ADDRESS R/W
UART0_RBR 0xFFF8_0000 R
UART0_THR 0xFFF8_0000 W
UART0_IER 0xFFF8_0004 R/W
UART0_DLL 0xFFF8_0000 R/W
UART0_DLM 0xFFF8_0004 R/W
UART0_IIR 0xFFF8_0008 R
UART0_FCR 0xFFF8_0008 W
UART0_LCR 0xFFF8_000C R/W
UART0_LSR 0xFFF8_0014 R
UART0_TOR 0xFFF8_001C R
DESCRIPTION
Receive Buffer Register (DLAB = 0)
Transmit Holding Register (DLAB = 0)
Interrupt Enable Register (DLAB = 0)
Divisor Latch Register (LS)
(DLAB = 1)
Divisor Latch Register (MS)
(DLAB = 1)
Interrupt Identification Register
FIFO Control Register
Line Control Register
Line Status Register
Time Out Register
RESET VALUE
0x0000_0000
0x0000_0080
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
RESET VALUE
0x0000_0000
0x0000_0000
RESET VALUE
Undefined
Undefined
0x0000_0000
0x0000_0000
0x0000_0000
0x8181_8181
Undefined
0x0000_0000
0x6060_6060
0x0000_0000
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