W90P710_05 Datasheet, PDF (54/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
EXTAL
INDV[4:0]
FIN
Input Divider
(NR)
PFD
Charge
Pump
PLL
VCO
Output _480MHz
Divider
(NO) ^FOUT
FBDV[8:0]
Feedback
Divider
(NF)
OTDV[1:0]
Fig 7.2.8.1 System PLL block diagram
The formula of output clock of PLL is:
FOUT
=
FIN
∗
NF
NR
∗
1
NO
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV + 2)
NF：Feedback divider value (NF = FBDV + 2)
NO：Output divider value (NO = OTDV)
USBCKS
GP0
1
48MHz
Gen
0
USB
Module
Clock
0
Divider
&
1
Selector
ECLKS
CLKS[2:0]
Internal
System
Clock
Clock Select Register (CLKSEL)
REGISTER ADDRESS
CLKSEL _{0xFFF0_000C}
R/W
R/W
DESCRIPTION
Clock Select Register
RESET VALUE
0x1FFF_7FX8
31
30
29
RESERVED
23
22
21
UART3
15
UART2
14
UART1
13
USBCKS
7
USBD
6
GDMA
5
USBH TIMER UART
28
PS2
20
I2C1
12
SDIO
4
ECLKS
27
KPI
19
I2C0
11
LCD
3
26
SCH1
18
RTC
10
EMC
2
CLKS
25
SCH0
17
PWM
9
RESERVED
1
24
SSP
16
AC97
8
WDT
0
RESET
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