W90P710_05 Datasheet, PDF (81/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[15]
ADRS
DESCRIPTION
Address bus alignment for external I/O bank 0~3
When ADRS is set, external address (A21~A0) bus is alignment to byte
address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is
AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.
[14:11]
tACC
Access cycles of external I/O bank 0~3
This parameter means nWE, nWBE and nOE active time clock. Detail timing
diagram please refer to Fig. 7.3.6 and 7.3.7
tACC[14:11]
MCLK
tACC[14:11]
MCLK
0 0 0 0 Reversed 1 0 0 0
9
0 00 1
1
1 001
11
0 01 0
2
1 010
13
0 01 1
3
1 011
15
0 10 0
4
1 100
17
0 10 1
5
1 101
19
0 11 0
6
1 110
21
0 11 1
7
1 111
23
[10:8]
Chip selection hold time of external I/O bank 0~3
This parameters control nWBE and nOE hold time. Detail timing diagram
please refer to Fig. 7.3.6 and 7.3.7
tCOH
tCOH [10:8]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MCLK
0
1
2
3
4
5
6
7
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Publication Release Date: January 17, 2005
Revision A.2