W90P710_05 Datasheet, PDF (91/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Write Hit：Data is written into both the cache and write buffer. The processor then continues to access
the cache, while the cache controller simultaneously downloads the contents of the write buffer to main
memory. This reduces the effective write memory cycle time from the time required for a main memory
cycle to the cycle time of the high-speed cache.
Write Miss：Data is only written into write buffer, not to the cache (write no allocate).
Data Cache Flushing
The W90P710 allows flushing of the data cache under software control. The data cache may be
invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register.
Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit
of the line is cleared to “0”. The D-cache is automatically flushed during reset.
Data Cache Load and Lock
The W90P710 supports a cache-locking feature that can be used to lock critical sections of data into D-
Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line
command.
To load and lock data, the following sequence should be followed:
1. Write the start address of the data to be locked into CAHADR register.
2. Set LDLK and DCAH bits in the CAHCON register.
3. Increased the address by 16 and written into CAHADR register.
4. Set LDLK and DCAH bits in the CAHCON register.
5. Repeat the steps 3 and 4, until the desired data are all locked.
When using D-Cache load and lock command, there are some notes should be cared.
y The programs executing load and lock operation should be held in a non-cacheable area of
memory.
y The cache should be enabled and interrupts should be disabled.
y Software must flush the cache before execute load and lock to ensure that the data to be locked
down is not already in the cache.
Data Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90P710 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the cache,
no operation is done and the command terminates with no exception. To unlock one line the following
unlock line sequence should be followed:
1. Write the address of the line to be unlocked into the CAHADR Register.
2. Set the ULKS and DCAH bits in the CAHCON register.
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Publication Release Date: January 17, 2005
Revision A.2