W90P710_05 Datasheet, PDF (261/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
31
30
23
22
15
14
7
6
Reserved
29
21
Reserved
13
5
HSIS
28
27
Reserved
20
19
12
4
VSIS
11
Reserved
3
VLFINIS2
26
18
UNDRIS2
10
2
VFFINIS2
25
17
UNDRIS1
9
1
VLFINIS1
24
16
AHBERIS
8
0
VFFINIS1
BITS
[31:20]
[18]
[17]
[16]
[15:6]
[5]
[4]
[3]
[2]
[1]
[0]
Reserved
UNDRIS2
UNDRIS1
AHBERIS
Reserved
HSIS
VSIS
VLFINIS2
VFFINIS2
VLFINIS1
VFFINIS1
DESCRIPTIONS
Reserved
FIFO2 have no data for output to Panel
FIFO1 have no data for output to Panel
AHB master bus error status
Reserved
Timing Generator output a HSYNC pulse
Timing Generator output a VSYNC pulse
FIFO2 transfer one line stream complete
FIFO2 transfer one frame stream complete
FIFO1 transfer one line stream complete
FIFO1 transfer one frame stream complete
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Publication Release Date: January 17, 2005
Revision A.2