W90P710_05 Datasheet, PDF (137/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[9]
[8]
[7]
[6]
[5]
EnDEN
EnDFO
DESCRIPTIONS
The Enable DMA Early Notification Interrupt controls the DENI
interrupt generation. If DENI of MISTA register is set, and both EnDEN
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DENI of MISTA register is set.
1’b0: DENI of MISTA register is masked from Rx interrupt generation.
1’b1: DENI of MISTA register can participate in Rx interrupt generation.
The Enable Maximum Frame Length Interrupt controls the DFOI
interrupt generation. If DFOI of MISTA register is set, and both EnDFO
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDFO or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DFOI of MISTA register is set.
1’b0: DFOI of MISTA register is masked from Rx interrupt generation.
1’b1: DFOI of MISTA register can participate in Rx interrupt generation.
EnMMP
The Enable More Missed Packet Interrupt controls the MMP interrupt
generation. If MMP of MISTA register is set, and both EnMMP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnMMP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the MMP of MISTA register is set.
1’b0: MMP of MISTA register is masked from Rx interrupt generation.
1’b1: MMP of MISTA register can participate in Rx interrupt generation.
EnRP
EnALIE
The Enable Runt Packet Interrupt controls the RP interrupt
generation. If RP of MISTA register is set, and both EnRP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the RP of MISTA register is set.
1’b0: RP of MISTA register is masked from Rx interrupt generation.
1’b1: RP of MISTA register can participate in Rx interrupt generation.
The Enable Alignment Error Interrupt controls the ALIE interrupt
generation. If ALIE of MISTA register is set, and both EnALIE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the ALIE of MISTA register is set.
1’b0: ALIE of MISTA register is masked from Rx interrupt generation.
1’b1: ALIE of MISTA register can participate in Rx interrupt generation.
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Publication Release Date: January 17, 2005
Revision A.2