W90P710_05 Datasheet, PDF (288/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[31:24]
[23:16]
[15:8]
[7:0]
Reserved
OSDRKYM
OSDGKYM
OSDBKYM
DESCRIPTIONS
Reserved
For color-key pattern mask of R component according to the source
color format
For color-key pattern mask of G component according to the source
color format
For color-key pattern mask of B component according to the source
color format
7.10.3.7.
LCD Timing Generation
LCD Timing Controller Register 1 (LCDTCON1)
REGISTER
ADDRESS R/W
DESCRIPTION
LCDTCON1 0xFFF0_80B0 R/W LCD Timing Control Register 1
RESET VALUE
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
HSPW_WLH
23
22
21
20
19
18
17
16
HSPW_WLH
HBPD_WDLY
15
14
13
12
11
10
9
8
HBPD_WDLY
HFPD_LINEBLANK
7
6
5
4
3
2
1
0
HFPD_LINEBLANK
BITS
[31:30]
Reserved
[29:20]
HSPW
WLH
[19:10]
HBPD
WDLY
DESCRIPTIONS
Reserved
TFT: Horizontal sync pulse width determines the HSYNC pulse's
high level width by counting the number of the VCLK.
STN: WLH bits determine the VLINE pulse's high level width by
counting the number of the LCDCLK.
TFT: Horizontal back porch is the number of VCLK periods between
the falling edge of HSYNC and the start of active data.
STN: WDLY bits determine the delay between VLINE and VCLK by
Counting the number of the LCDCLK.
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