W90P710_05 Datasheet, PDF (21/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Table 5.1 W90P710 Pins Description (Continued)
Pin Name
Ethernet Interface
PHY_MDC /
GPIO [51] /
KPROW[1] /
LCD_VD[17]
IO
Type
IOU
PHY_MDIO /
GPIO [50] /
IO
KPROW[0] /
LCD_VD[16]
PHY_TXD [1:0] /
GPIO [49:48] /
IOU
KPCOL[7:6] /
LCD_VD[15]
PHY_TXEN /
GPIO [47] /
IOU
KPCOL[5] /
LCD_VD[14:13]
PHY_REFCLK /
GPIO [46] /
KPCOL[4] /
IOS
LCD_VD[12]
PHY_RXD [1:0] /
GPIO [45:44] /
IOS
KPCOL[3:2] /
LCD_VD[11:10]
PHY_CRSDV /
GPIO [43] /
IOS
KPCOL[1] /
LCD_VD[9]
PHY_RXERR /
GPIO [42] /
IOS
KPCOL[0] /
LCD_VD[8]
Description
RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.
Each MDIO data will be latched at the rising edge of MDC clock.
General Programmable In/Out Port [51]
Keypad ROW[1] scan output.
LCD VD[17] data output
RMII Management Data I/O for Ethernet. It is used to transfer RMII control and
status information between PHY and MAC.
General Programmable In/Out Port [51]
Keypad ROW[0] scan output.
LCD VD[16] data output.
2-bit Transmit Data bus for Ethernet.
General programmable In/Out Port [49:48]
Keypad Column input [7:6], active low
LCD VD[15] data output
PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble
and shall remain asserted while all di-bits to be transmitted are presented. Of
course, it is synchronized with PHY_REFCLK.
General Programmable In/Out Port [47]
Keypad column input [5], active low
LCD VD[14:13] data output.
Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%
duty cycle at high or low state.
General Programmable In/Out port [46]
Keypad column input [4], active low
LCD VD[12] data output.
2-bit Receive Data bus for Ethernet.
General Programmable In/Out Port [45:44]
Keypad column input [3:2], active low
LCD VD[11:10] data output.
Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be
asserted by PHY when the receive medium is non-idle. Loss of carrier shall
result in the de-assertion of PHY_CRSDV synchronous to the cycle of
PHY_REFCLK, and only on 2-bit receive data boundaries.
General Programmable In/Out port [43]
Keypad column input [1], active low
LCD VD[9] data output.
Receive Data Error for Ethernet. It indicates a data error detected by PHY.The
assertion should be lasted for longer than a period of PHY_REFCLK. When
PHY_RXERR is asserted, the MAC will report a CRC error.
General programmable In/Out port [42]
Keypad column input [0], active low
LCD VD[8] data output.
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Publication Release Date: January 17, 2005
Revision A.2