W90P710_05 Datasheet, PDF (438/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued
BITS
[5:3]
[2]
[1]
[0]
DESCRIPTIONS
PEC2, PEC1,
PEC0
Parity Error Count.
Bits PEC2, PEC1 and PEC0 determine the number of allowed
repetitions in reception or in transmission before setting bit PBER in
SCSR.
The value 000 indicates that, if only one parity error has occurred, bit PE
is set; the value 111 indicate that bit PE will be set after 8 parity errors.
In protocol T =0:
If a correct character is received before the programmed error number is
reached, the error counter will be reset
If the programmed number of allowed parity errors is reached, bit PBER
in register SCSR will be set as long as register SCSR has not been
read.
If a transmitted character has been NAK by the card, then our smart
card host interface will automatically re-transmit it a number of times
equal to the value programmed in bits PEC2, PEC1 and PEC0.
In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then
the automatic re-transmission is invalided; the character manually
rewritten in register TBR will start at 13.5 ETU.
In protocol T= 1:
The error counter has no action; bit PE is set at the first incorrectly
received character.
TxFRST
Transmitter FIFO Reset control bit.
Setting this bit to a logical "1" resets the transmitter FIFO counter to
initial state. This bit is self-cleared to "0" after being set to "1". Default
is "0".
RxFRST
Receiver FIFO Reset control bit.
Setting this bit to a logical "1" resets the receiver FIFO counter to initial
state. This bit is self-cleared to "0" after being set to "1". Default is "0".
RESERVED -
Smart Card Control Register (SCHI_SCCR)
REGISTER
SCHI_SCCR0
SCHI_SCCR1
ADDRESS
0xFFF8_500C
0xFFF8_580C
R/W
R/W
R/W
DESCRIPTION
Smart Card Control Register 0
Smart Card Control Register 1
RESET VALUE
0x0000_0018
0x0000_0018
- 438 -