W90P710_05 Datasheet, PDF (93/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
RESERVED
WRBEN DCAEN ICAEN
BITS
[31:3]
[2]
[1]
[0]
RESERVED
WRBEN
DCAEN
ICAEN
DESCRIPTION
-
Write buffer enable
Write buffer is disabled after reset.
1 = enable write buffer
0 = disable write buffer
D-Cache enable
D-Cache is disabled after reset.
1 = enable D-cache
0 = disable D-cache
I-Cache enable
I-Cache is disabled after reset.
1 = enable I-cache
0 = disable I-cache
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y Flush I-Cache and D-Cache
y Load and lock I-Cache and D-Cache
y Unlock I-Cache and D-Cache
y Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
- 93 -
Publication Release Date: January 17, 2005
Revision A.2