W90P710_05 Datasheet, PDF (110/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
REGISTER ADDRESS
R/W
DESCRIPTION
CONTROL REGISTERS (44)
CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register
CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register
CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register
CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register
CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register
CAM14L 0xFFF0_307C R/W CAM14 Least Significant Word Register
CAM15M 0xFFF0_3080 R/W CAM15 Most Significant Word Register
CAM15L 0xFFF0_3084 R/W CAM15 Least Significant Word Register
TXDLSA
0xFFF0_3088
R/W
Transmit Descriptor Link List Start
Address Register
RXDLSA
0xFFF0_308C
R/W
Receive Descriptor Link List Start
Address Register
MCMDR 0xFFF0_3090 R/W MAC Command Register
MIID
0xFFF0_3094 R/W MII Management Data Register
MIIDA
0xFFF0_3098
R/W
MII Management Control and Address
Register
FFTCR
0xFFF0_309C R/W FIFO Threshold Control Register
TSDR
0xFFF0_30A0 W Transmit Start Demand Register
RSDR
0xFFF0_30A4 W Receive Start Demand Register
DMARFC
0xFFF0_30A8
R/W
Maximum Receive Frame Control
Register
MIEN
0xFFF0_30AC R/W MAC Interrupt Enable Register
Status Registers (11)
MISTA
0xFFF0_30B0 R/W MAC Interrupt Status Register
MGSTA
0xFFF0_30B4 R/W MAC General Status Register
MPCNT
0xFFF0_30B8 R/W Missed Packet Count Register
MRPC
0xFFF0_30BC R MAC Receive Pause Count Register
MRPCC
0xFFF0_30C0
R
MAC Receive Pause Current Count
Register
MREPC
0xFFF0_30C4 R MAC Remote Pause Count Register
DMARFS 0xFFF0_30C8 R/W DMA Receive Frame Status Register
RESET VALUE
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xFFFF_FFFC
0xFFFF_FFFC
0x0000_0000
0x0000_0000
0x0090_0000
0x0000_0101
Undefined
Undefined
0x0000_0800
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_7FFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
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