M16C6K9 Datasheet, PDF (97/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial I/O
Serial I/O
Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.
UART0 to 2
Each of UART0 - UART2 has an exclusive timer to generate a transfer clock, operating independently from
each other.
Fig.GA-1 shows the block diagram of UART0, UART1 and UART2. Fig.GA-2 and GA-3 show the block
diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode selection bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode
(Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and
the RxD pin are different in level.
Table.GA-1 shows the comparison of functions of UART0 through UART2, and Fig.GA-4 to GA-8 show the
registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table.GA-1 Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
CLK polarity selection
Possible (Note 1) Possible (Note 1) Possible (Note 1)
LSB first / MSB first selection
Possible (Note 1) Possible (Note 1) Possible (Note 2)
Continuous receive mode selection
Transfer clock output from multiple
pins selection
Separate CTS/RTS pins
Possible (Note 1) Possible (Note 1) Possible (Note 1)
Impossible
Possible (Note 1) Impossible
Possible
Impossible
Impossible
Serial data logic switch
Sleep mode selection
Impossible
Impossible
Possible (Note 4)
Possible (Note 3) Possible (Note 3) Impossible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Impossible
CMOS output
Impossible
Impossible
CMOS output
Impossible
Possible
N-channel open-drain
output
Possible (Note 4)
Bus collision detection
Impossible
Impossible
Note 1: Only in clock synchronous serial I/O mode.
Note 2: Only in clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only in UART mode.
Note 4: Can be used for SIM interface.
Rev.1.00 Jun 06, 2003 page 97 of 290
Possible