M16C6K9 Datasheet, PDF (53/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC)
are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Fig.DD-7 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM
instruction alone can save all the registers except the stack pointer (SP).
Address
Stack area
MSB
LSB
m–4
m–3
m–2
m–1
m
Content of previous stack
m + 1 ^{Content of previous stack}
[SP]
Stack pointer
value before
interrupt occurs
Address
Stack area
MSB
LSB
m–4
m–3
Program counter (PCL)
Program counter (PCM)
m–2
Flag register (FLGL)
m – 1 ^{Flag register Program}
(FLGH) counter (PCH)
m
Content of previous stack
m + 1 Content of previous stack
[SP]
New stack
pointer value
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Fig.DD-7 State of stack before and after acceptance of interrupt request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content
of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the
stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter
(PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Fig.DD-8
shows the operation of the saving registers.
Note: Stack pointer is indicated by U flag when software number 32 - 63 INT command is executed,
otherwise is indicated by ISP.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even) ^{Program counter (PCL)}
[SP] – 3 (Odd) Program counter (PCM)
[SP] – 2 (Even) Flag register (FLGL)
[SP] – 1 (Odd)
Flag register Program
(FLGH) ^{counter (PCH)}
[SP] (Even)
[SP] – 5 (Even)
(2) Saved simultaneously,
all 16 bits
[SP] – 4 (Odd)
[SP] – 3 (Even)
Program counter (PCL)
Program counter (PCM)
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
[SP] – 2 (Odd) Flag register (FLGL)
[SP] – 1
(Even)
Flag register Program
(FLGH) ^{counter (PCH)}
[SP] (Odd)
(3)
(4) Saved
simultaneously,
(1) _{all 8 bits}
(2)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Fig.DD-8 Operation of saving registers
Rev.1.00 Jun 06, 2003 page 53 of 290