M16C6K9 Datasheet, PDF (223/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
PS2 Interface
q Transfer abort operation
Fig.GK-11 shows the transfer abort operation timing.
1
2
3
3
3
3
45
6
DAT
CLK
(Device side CLK)
(Controller side CLK)
Transfer abort request bit
Reception abort incognizable flag
Transfer abort completion flag
Transfer completion flag
Interrupt request
start ^{D0 D1 D2 D3 D4}
Fig.GK-11 Transfer abort operation timing ( reception)
(1) - (3) Data reception operation
(4) Transfer abort request
Set 0416 (transfer abort request bit = “1”) to PS2i control register (address : 02A216, 02A616,02AA16).
(5) Transfer abort completion
The transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register
(address : 02A116, 02A516, 02A916) are set to “1”, transfer abort request bit (bit 2) of PS2i control register
(address : 02A216, 02A616, 02AA16) is cleared to “0”. At this time, PS2 clock (CLK) becomes “L” (recep-
tion disable status) and interrupt request occurs.
(6) Status clear
By a pseudo read of PS2i shift register (address : 02A016, 02A416, 02A816), the transfer abort completion
flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A116, 02A516, 02A916)
are cleared to “0”.
Note: Do not execute the following transmission/reception during the period between the “L” output from
PS2 clock (CLK) and the transfer abort request recognition of the device.
Rev.1.00 Jun 06, 2003 page 223 of 290