M16C6K9 Datasheet, PDF (185/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
I²C Control Register 0
The I²C control register 0 (address 032316, 033316, 031316) of channel 0, 1 controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. The I²C interrupt request
signal occurs immediately after the number of count specified with these bits (ACK clock is added to the
number of count when ACK clock is selected by ACK bit (bit 7 of address 032416, 033416, 031416)) have
been transferred, and BC0 to BC2 are returned to “0002”.
Also when a START condition is detected, these bits become “0002” and the address data is always trans-
mitted and received in 8 bits.
•Bit 3: I²C interface enable bit (ES0)
This bit enables to use the multi-master I²C-BUS interface. When this bit is set to “0”, the interface is disabled
and the SDA and the SCL become high-impedance. When the bit is set to “1”, the interface is enabled.
When ES0 = “0”, the following is performed.
1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I²C status
register (Address : 032816, 033816, 031816)
2)Writing data to I²C data shift register (Address : 032016, 033016, 031016) is inhibited.
3)The TOF bit of I²C control register (Address : 032716, 033716, 031716) is cleared to “0”
4)I²C system clock (VIIC) is stopped and the interval counter, flags are initialized.
•Bit 4: Data format selection bit (ALS)
This bit decides if the recognition of slave address should be processed. When this bit is set to “0”, the
addressing format is selected, so that address data will be recognized. The transfer will be processed only
when a comparison is matched between the salve address and the address data or a general call is received
(refer to the item of bit 1 of I²C status register: general call detection flag). When this bit is set to “1”, the free
data format is selected, so that slave address will not be not recognized.
•Bit 5: Addressing format selection bit (DBIT SAD)
This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format
is selected. In this case, only the high-order 7 bits (slave address) of the I²C address register (address
032216, 033216, 031216) are compared with address data. When this bit is set to “1”, the 10-bit ad-
dressing format is selected, and all the bits of the I²C address register are compared with address data.
•Bit 6: I²C-BUS interface reset bit (IHR)
The bit is used to reset I²C-BUS interface circuit in the case that the abnormal communication occurs.
When the ES0 bit is“1” (I²C-BUS interface is enabled), writing“1” to the IHR bit makes a H/W reset.
Flags are processed as follows:
1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I²C status
register (Address : 032816, 033816, 031816)
2)The TOF bit of I²C control register (Address : 032716, 033716, 031716) is cleared to “0”
3)The interval counter, flags are initialized.
After writing“1” to IHR bit, the circuit reset processing will be finished in Max. 2.5 VIIC cycles and IHR bit will
be automatically cleared to “0”. Fig.GC-6 shows the reset timing.
•Bit 7: I²C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multi-master I²C-BUS interface. When this bit is
set to“1” the P60,P61/P62,P63/P76,P77 will become SMBus input level.
Rev.1.00 Jun 06, 2003 page 185 of 290