M16C6K9 Datasheet, PDF (65/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt
enable flag (I flag) and processor interrupt priority level (IPL). The stacked value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Fig.DD-20 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
Bit symbol
AIER0
Bit name
Address match interrupt 0
enable bit
AIER1 Address match interrupt 1
enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
RW
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
Symbol
b0
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
Function
Values that can be set R W
Address setting register for address match interrupt 0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Fig.DD-20 Address match interrupt-related registers
Rev.1.00 Jun 06, 2003 page 65 of 290