M16C6K9 Datasheet, PDF (221/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
PS2 Interface
q Reception operation
Fig.GK-9 shows the reception operation timing.
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DAT
CLK
(Device side CLK)
(Controller side CLK)
Reception enable bit
Data receiving flag
Reception abort incognizable flag
Transfer completion flag
Interrupt request
start D0 D1 D2 D3 D4 D5 D6 D7 parity stop
Fig.GK-9 Reception operation timing
(1) Reception enable
The reception operation is enabled by writing 0116 (reception enable bit = “1”) to PS2i control register
(address : 02A216, 02A616, 02AA16). The PS2 clock (CLK) will become “H”.
(2) Reception start
The reception operation starts when both PS2 clock (CLK) and PS2 data (DAT) are detected with “L”.
(3) Data reception (The reception of data and parity bits)
The content PS2 data (DAT) is read into PS2i shift register (address : 02A016, 02A416, 02A816) sequentially
by the falling edge of PS2 clock (CLK). The data transfer sequence is data bit (D0 -D7) then parity bit.
(4) Reception completion (Stop bit Reception completion)
By detecting the falling edge of PS2 clock (CLK), the transfer completion flag (bit 0 of PS2i status register)
is set to “1” after the update of error flag (bit 4 - 6 of PS2i status register) and the reception enable bit
(bit 0 of PS2i control register) is cleared to “0”. The PS2 clock (CLK) becomes “L” (reception disable
status) and interrupt request occurs.
(5) Data read out
Read out data from PS2i shift register (address : 02A016,02A416,02A816). At this time , the error flags
(Bit4 to 6) of and transfer completion flag (bit 0) of PS2i status register (address: 02A116, 02A516, 02A916)
will be cleared to “0”.
Rev.1.00 Jun 06, 2003 page 221 of 290