M16C6K9 Datasheet, PDF (143/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Comparator
Comparator Circuit
Comparator Configuration
A comparator circuit consists of a switch tree, ladder resistance, comparators, comparator control circuit, the
comparator control register (address 03DE16), comparator data register (address 03DF16), and analog signal
input pins(P50 - P57). The analog input pins (P50 - P57) are shared with the usual digital port I/O pins.
The comparator control register is a 4-bit register and can generate internal analog voltages in steps of 1/16
Vcc with the contens of bits 0 to 3. In Table.JC-2 contents of bits 0 to 3 of the comparator control register
and corresponding internal analog voltage generated are indicated. The compared result of the analog
input voltage and internal analog voltage is stored in the comparator data register. The value of comparator
control register can not be read out.
Comparator Operation
In order to perform comparator operation, first, set the port P5 direction register (address 03EB16) to "0", as
P5 can be used as the analog input pins. Then write a digital value, which corresponds to the internal
analog voltage to be compared, to bits 0 to 3 of the comparator control register (address 03DE16) . The
voltage comparison starts immediately by the writing operation. After 28 cycles of main clock without division
(the cycles needed for comparison, no relation to the frequency), the compared result of the comparator is stored
in the comparator data register (address 03DF16). Each bit of this register becomes as follows depending on the
status of corresponding P50 to P57 pins:
When analog input voltage > internal analog voltage, it is "1".
When analog input voltage < internal analog voltage, it is "0".
For comparing once more, it is necessary to write data into comparator control register again even if the
internal analog voltage is the same.
To read the result, wait 28 cycles of main clock without division (the cycles needed for comparison, no
relation to the frequency) or more after the comparator operation starts.
During the 28 cycles of the comparison, the ladder resistance is turned on and the reference voltage is
generated. When the comparator is not in operation, the ladder resistance is off. Therefore, unnecessary
consumption is prevented.
The comparison is accomplished by capacitive coupling. If the clock frequency is too low, electric charge
will be lost. While the comparator is in operation, the clock frequency must be 1MHz or higher. During this
time, do not execute a STP instruction, a WIT instruction, or an I/O instruction for port P5.
8
P5 (8)
P57
P56
Data bus
8
Comparator data
register(03DF16)
Compa
rator
Compa
rator
4
Comparator control
register(03DE16)
b0
b3
b0
R-ladder
P50
Fig.JC-1 Comparator circuit
Compa
rator
Switch Tree
Comparator
Comparator connection ^{Control Cricuit}
signal
R-ladder connection
signal
VSS
Rev.1.00 Jun 06, 2003 page 143 of 290