M16C6K9 Datasheet, PDF (197/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
I²C START/STOP condition control register
I²C START/STOP condition register(address 032516, 033516, 031516) controls the detection of START/STOP
condition.
•Bit0-Bit4: START/STOP condition setting bits (SSC4-SSC0)
Because the release time, set up time and hold time of SCL is calculated on the base of I²C system clock(VIIC).
The detecting condition changes depending on the oscillation frequency and I²C system clock selecting bits. It
is necessary to set the suitable value of START/STOP condition setting bits (SSC4-SSC0) so that obtain the
release time, set up time and hold time corresponding to the system clock frequency. Refer to Table GC-11. Do
not set odd number or “000002” to START/STOP condition setting bits. The recommended setting value to
START/STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode is
shown in Table. GC-8. The detection of START/STOP condition starts immediately after the setting of ES0=1.
•Bit5: SCL/SDA interrupt pin polarity selection bit (SIP)
The interrupt can be generated by detecting the rising edge or the falling edge of SCL pin or SDA pin. SCL/SDA
interrupt pin polarity selection bit selects the polarity of SCL pin or SDA pin for interrupt.
•Bit6 : SCL/SDA interrupt pin selection bit (SIS)
SCL/SDA interrupt pin selection bit selects either SCL pin or SDA pin as SCL/SDA interrupt enable pin.
Note: The SCL/SDA interrupt request may be set when the setting of I²C-BUS interface enable bit ES0 changes.
Thus set the interrupt disable before the setting of SCL/SDA interrupt pin polarity selection bit (SIP) and
SCL/SDA interrupt selection bit(SIS). After that reset “0” to the interrupt request bit before enabling the
interrupt.
•Bit7: START/STOP condition generation selecting bit (STSPSEL)
The bit selects the length of set up/hold time when START/STOP condition occurs. The length of set up/hold
time is based on the I²C system clock cycles. Refer to Table GC-9. Set the bit to “1” if I²C system clock frequency
is over 4MHz.
Rev.1.00 Jun 06, 2003 page 197 of 290