M16C6K9 Datasheet, PDF (130/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
S I/O3, 4
Functions for setting an SOUTi initial value
In carrying out transmission, the output level of the SOUTi pin as it is before transmitting 1-bit data can be set
either to “H” or to “L”. Fig.GA-30 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) With "H" selected for SOUTi
Signal written to the SI/Oi
transmission /reception
register
SOUTi's initial value
set bit (SMi7)
SI/Oi port selection bit
(SMi3)
D0
SOUTi (internal)
SOUTi pin output
Port output
D0
Initial value = "H"(Note)
(i = 3, 4)
Setting the SOUTi initial Port selection
value to H (normal port SOUTi)
Note: The set value is output only when the external clock has been selected. Please
set the SOUTi default under the status that the CLKi is input to "H" level.
If the internal clock has been selected or if SOUTi output inhibition has been set,
this output goes to the high-impedance state.
SI/Oi port selection bit SMi3 = 0
SOUTi initial value selection bit
SMi7 = 1
(SOUTi: Internal "H" level)
SI/Oi port selection bit
SMi3 = 0 1
(Port selection: Normal port SOUTi)
SOUTi pin = "H" output
Signal written to the SI/Oi register
="L" "H" "L"
(Falling edge )
SOUTi pin = Outputting
stored data in the SI/Oi transmission/
reception register
Fig.GA-30 Timing chart for setting SOUTi’s initial value and how to set it
S I/Oi operation timing
Fig.GA-31 shows the S I/Oi operation timing
MAX:1.5 cycle
SI/Oi internal clock
Transfer clock
(Note 1)
Signal written to the
SI/Oi register
S I/Oi output SOUTi
(i= 3, 4)
SI/Oi input SINi
(i= 3, 4)
SI/Oi interrupt ^"1"
request bit (i=3,4)
"0"
Hiz
D0
D1
D2
D3
D4
D5
D6
(Note 2)
D7 ^Hiz
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the
SI/Oi control register (i = 3,4). (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3,4) pin becomes to the high-impedance state after the
transfer finishes.
Note 3: The figure shows when the port selection bit of SOUTi (i = 3,4) is set to "1".
Fig.GA-31 S I/Oi operation timing chart
Rev.1.00 Jun 06, 2003 page 130 of 290