M16C6K9 Datasheet, PDF (152/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
Figure GF-3 Shows Data bus buffer control registers
Figure GF-4 Shows Data bus buffer status register
Figure GF-5, 6 Shows LPC related registers
Data bus buffer status register (DBBSTS0-DBBSTS3)
This is 8-bit register.
The bit 0, 1, 3 are read only bits and indicate the status of data bus buffer.
Bit 2, 4, 5, 6, 7 are user definable and flags which can be read and written by software. The data bus buffer
status register can be read out by host CPU when the slave address (16 bit) bit2 (A2) is high.
• Output buffer full flag (OBF)
The bit will be set to “1” when a data is written into output data bus buffer and will be cleared to “0” when host
CPU read out the data from output data bus buffer.
• Input buffer full flag (IBF)
The bit will be set to “1” while a data is written into input data bus buffer by host CPU and will be cleared to
“0”when the data is read out from input data bus buffer by slave CPU.
• XA2 flag (XA2)
The bit 2 of slave address (16 bits) is latched while a data is written into data bus buffer.
Input data bus buffer register (DBBIN0-DBBIN3)
When there is a write request from host CPU, the data on the data bus will be latched to DBBIN0-3. The data
of DBBIN0-3 can be read out from data bus buffer registers (Address:02C016, 02C216 , 02C416 , 02C616 ) in
SFR field.
Output data bus buffer register (DBBOUT0-DBBOUT3)
When writing data to data bus buffer registers (Address: 02C016 , 02C216 , 02C416 , 02C616 ), the data will
be transferred to DBBOUT0-3 automatically. The data of DBBOUT0-3 will be output to the data bus when
there is a read request from host CPU and the status of bit2 (A2) of slave address (16 bits) is low.
LPCi address register H/L (LPC1ADH-LPC3ADH / LPC1ADL-LPC3ADL)
The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h.
The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC1-3 address regis-
ters H/L (02D016 to 02D516 ). The settings are for slave address upper 8 bits and lower 8 bits. And these
registers can be set and cleared in any time.
The bit 2 of LPC 1-3 address L is not decoded regardless of the setting value. When slave CPU reads LPC1-
3 address registers, the bit2 (A2) of address low byte will be fixed to “0”. The bit2 (A2) status of slave address
is latched to XA2 flag when written by host CPU. The slave addresses that are already set in these registers
will be used for comparing with the addresses to be received.
Rev.1.00 Jun 06, 2003 page 152 of 290