M16C6K9 Datasheet, PDF (182/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
I²C Clock Control Register
The I²C clock control register 0,1 (address 032416, 033416, 031416) is used to set ACK control, SCL mode
and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table GC-2.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit
is set to “1” , the high-speed clock mode is selected. When connecting to the bus with the high-speed mode
I²C-BUS standard (maximum 400 kbits/s), set 4 MHz or more to I²C system clock(VIIC).
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock is generated. When this bit is set to “0”, the ACK return mode
is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK
nonreturn mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However,
when the slave address agrees with the address data in the reception of address data at ACK BIT = “0”, the
SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and
the address data, the SDA is automatically made “H” (ACK is not returned).
*ACK clock: Clock for acknowledgment
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which responses to the data transferring. When this bit is set
to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When
the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock at the comple-
tion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA
at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving
device.
Note: Except for ACK bit (ACKBIT), do not write data into the I²C clock control register during transfer.
If data is written during transfer, the I²C clock generator is reset, so that data cannot be transferred
normally.
Rev.1.00 Jun 06, 2003 page 182 of 290