M16C6K9 Datasheet, PDF (123/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, an “L” level from the TxD2 pin
will be output when a parity error is detected. Link with this function, the timing to generate a transmission
completion interrupt varies according to the timing of a parity error signal detection. Fig.GA-23 shows the
timing of the parity error signal output.
• LSB first
Transfer “H”
clock ^{“L”}
RxD2 “H”
“L”
TxD2 ^{“H”}
“L”
Receive “1”
complete flag ^{“0”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Hi-Z
Fig.GA-23 Timing of the parity error signal output
ST : Start bit
P : Even parity
SP : Stop bit
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the
direct format, data are output from TxD2 beginning with D0. If you choose the inverse format, data are
inverted and output from TxD2 beginning with D7.
Fig.GA-24 shows the SIM interface format.
Transfer clcck
TxD2
(direct)
TxD2
(inverse)
D0 D1 D2 D3 D4 D5 D6 D7 P
D7 D6 D5 D4 D3 D2 D1 D0 P
P : Even parity
Fig.GA-24 SIM interface format
Rev.1.00 Jun 06, 2003 page 123 of 290