M16C6K9 Datasheet, PDF (159/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
<2> Example for I/O reading cycle from HOST
Reading timing is shown in Figure GF-9.
The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the
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rising edge of LCLK. Communication will start from LFRAME falling edge.
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• 1^st cycle: When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start detecting.
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• 2^ndcycle: When LFRAME is "High", the host send "000X2 " on LAD[3:0] to inform the cycle type as I/O read.
• From 3^rd cycle to 6^thcycle: These four cycles are detecting for 16 bits slave address.
3^rdcycle: The slave address which is from host is written to slave address register [15:12] throughLAD[3:0]
4^thcycle: The slave address which is from host is written to slave address register [11:8] throughLAD[3:0]
5^thcycle: The slave address which is from host is written to slave address register [7:4] throughLAD[3:0]
6^thcycle: The slave address which is from host is written to slave address register [3:0] throughLAD[3:0]
• 7^th and 8^thcycles are used for changing the communication direction from host→slave to slave→host
7^thcycle: Host is output "11112 " to LAD[3:0]
8^thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 9^thcycle : The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 10^th and 11^thcycles are for output 8 bits data from output data buffer or output 8 bits data from status register.
10^thcycle: Sending output data buffer [3:0] to LAD[3:0] or sending data of status register [3:0] to LAD[3:0]
11^thcycle: Sending output data buffer [7:4] to LAD[3:0] or sending data of status register [7:4] to LAD[3:0].
• 12^thcycle: The "11112 " is output to LAD[3:0]. The OBF flag is cleared and OBE interrupt signal is generated.
• 13^thcycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. OBF flag will be
set when 8 bits data are written to output data buffer by slave CPU.
Rev.1.00 Jun 06, 2003 page 159 of 290