M16C6K9 Datasheet, PDF (184/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
Table.GC-2 Set values of I²C clock control register and SCL frequency
Setting value of CCR4 to CCR0
SCL frequency (at VIIC=4MHz, unit : kHz) (Note1)
CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode
High-speed clock mode
0
0
00
0
Setting disabled
Setting disabled
0
0
00
1
Setting disabled
Setting disabled
0
0
01
0
Setting disabled
Setting disabled
0
0
01
1
- (Note2)
333
0
0
10
0
- (Note2)
250
0
0
10
1
100
400 (Note3)
0
0
11
0
83.3
166
500 / CCR value
1000 / CCR value
(Note3)
(Note3)
1
1
10
1
17.2
34.5
1
1
11
0
16.6
33.3
1
1
11
1
16.1
32.3
Notes1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock
mode is selected and CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H” duration of the clock
fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2
machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency
does not increase because “L” duration is extended instead of “H” duration reduction. These are
value when SCL clock synchronization by the synchronous function is not performed. CCR value
is the decimal notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these
setting value, use VIIC = 4 MHz or less. Refer to I²C system clock selection bits (bit 6,7 of
I²C control register 1) on VIIC.
3: The data formula of SCL frequency is described below:
VIIC/(8 X CCR value) Standard clock mode
VIIC/(4 X CCR value) High-speed clock mode (CCR value ≠ 5)
VIIC/(2 X CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of VIIC frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock
mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
Rev.1.00 Jun 06, 2003 page 184 of 290