M16C6K9 Datasheet, PDF (36/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Status Transition Of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table.WA-4 shows the operating modes corresponding to the settings of system clock control regis-
ters 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting from high speed mode or mid-speed
mode to stop mode, and after a reset main clock division select bit 0 (bit 6 at address 000616) is set to “1”. It
is matained in low speed mode and low power dissipation mode.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. After reset, it works in this mode. Note that oscillation of
the main clock must have stabilized before transferring from this mode to No-division, Division by 2 and
Division by 4 mode. Oscillation of the sub clock must have stabilized before transferring this mode to Low-
speed mode and Low power dissipation mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock
starts. Therefore, the program must be written to wait until this clock has stabilized immediately after power-
ing up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Precaution
In the case of switching the BCLK count source from XIN to XCIN, or from XCIN to XIN, it is necessary that the
destination clock count source be stable. The transition should be waited by software after the oscillation
being stable.
Table.WA-4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
1
0
0
0
Invalid Division by 2 mode
1
0
0
0
0
Invalid Division by 4 mode
Invalid Invalid
0
1
0
Invalid Division by 8 mode
1
1
0
0
0
Invalid Division by 16 mode
0
0
0
0
0
Invalid No-division mode
Invalid Invalid
1
Invalid
0
1
Low-speed mode
Invalid Invalid
1
Invalid
1
1
Low power dissipation mode
Rev.1.00 Jun 06, 2003 page 36 of 290