M16C6K9 Datasheet, PDF (265/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
CPU Reprogram Mode
Precautions on CPU reprogram mode
Described below are the precautions to be observed in programming the flash memory in CPU reprogram
mode.
(1) Operation speed
During CPU reprogram mode, set the main clock frequency as shown below using the main clock divide ratio
select bits (bit 6 at address 000616 and bit 6 and 7 at address 000716):
Not exceeding 8MHz if wait bit (bit 7 of address 000516) = “0”. (No wait for internal accessing)
Not exceeding 16MHz if wait bit (bit 7 of address 000516) = “1”. (1 wait for internal accessing)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU reprogram mode because they refer to the internal
data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction
(3) Interrupts inhibited against use
_______
The NMI, address match and WDC interrupts cannot be used during CPU reprogram mode because they
refer to the internal data of the flash memory. If interrupts have their vectors in the variable vector table, they
can be used by transferring the vector into the RAM area.
(4) Reset
The reset is always receivable.
(5) The reprogram in user ROM area
When CPU reprogram mode is entered and the block that the flash reprogram control program is located is
being reprogramming, the block may not be reprogrammed correctly if the power supply is suddenly down. It
is possible that the flash reprogram cannot be executed again in this case. Thus, it is recommended to use
standard serial I/O mode and parallel I/O mode.
Rev.1.00 Jun 06, 2003 page 265 of 290