M16C6K9 Datasheet, PDF (112/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial I/O
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows to set two transfer clock output pins and chooses one to output a clock by the setting of
CLK and CLKS selection bits (bits 4 and 5 at address 03B016). (See Fig.GA-13) The function is valid only
_______ _______
when the UART1 internal clock is selected. Note that when this function is selected, UART1 CTS/RTS
function cannot be used.
Microcomputer
TXD1
CLKS1
CLK1
IN
IN
CLK
CLK
Fig.GA-13 The sample of transfer clock output from the multiple pins function
(d) Continuous receive mode
If the continuous receive mode enable bits (bits 2 and 3 at address 03B016, bit 5 at address 037D16) are set
to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read
out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit
buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of
setting and the input/output pin functions are both the same, so refer to the selection function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the transfer
clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2)
When the data logic selection bit (bit6 at address 037D16) = “1”, the data writing to transmit buffer register or
reading from receive buffer register, are reversed. Fig.GA-14 shows the example of serial data logic switch
timing.
•When LSB first
Transfer clock ^{“H”}
“L”
TxD2 “H”
(no reverse) _{“L”}
TxD2 “H”
(reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Fig.GA-14 Serial data logic switch timing
Rev.1.00 Jun 06, 2003 page 112 of 290