M16C6K9 Datasheet, PDF (23/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
SFR
SFR
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
DMA0 source pointer (SAR0)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
I²C2 interrupt control register (IIC2IC)
SCL2,SDA2 interrupt control register (SCLDA2IC)
DMA0 interrupt control register (DM0IC)
Timer B5 interrupt control register (TB5IC)
LRESET interrupt control register (LRSTIC)
INT3 interrupt control register (INT3IC)
INT9 interrupt control register (INT9IC)
Timer B4 interrupt control register (TB4IC)
UART1 receive interrupt control register (S1RIC)
SI/O4 interrupt control register (S4IC)
Timer B3 interrupt control register (TB3IC)
UART1 transmit interrupt control register (S1TIC)
SI/O4 interrupt control register (S4IC)
INT6 interrupt control register (INT6IC)
SI/O3 interrupt control register (S3IC)
INT5 interrupt control register (INT5IC)
Bus collision detection interrupt control register (BCNIC)
INT4 interrupt control register (INT4IC)
INT8 interrupt control register (INT8IC)
DMA1 interrupt control register (DM1IC)
INT7 interrupt control register (INT7IC)
Key input interrupt 0 control register (KUP0IC)
A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC)
IBF0 interrupt control register (IBF0IC)
UART2 receive interrupt control register (S2RIC)
IBF1 interrupt control register (IBF1IC)
UART0 transmit interrupt control register (S0TIC)
I²C0 interrupt control register (IIC0IC)
UART0 receive interrupt control register (S0RIC)
SCL0,SDA0 interrupt control register (SCLDA0IC)
INT11 interrupt control register (INT11IC)
UART1 transmit interrupt control register (S1TIC)
I²C1 interrupt control register (IIC1IC)
UART1 receive interrupt control register (S1RIC)
SCL1,SDA1 interrupt control register (SCLDA1IC)
INT10 interrupt control register (INT10IC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
INT7 interrupt control register (INT7IC)
SI/O3 interrupt control register (S3IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
IBF2 interrupt control register (IBF2IC)
Timer A4 interrupt control register (TA4IC)
IBF3 interrupt control register (IBF3IC)
Timer B0 interrupt control register (TB0IC)
SCL0,SDA0 interrupt control register (SCLDA0IC)
INT11 interrupt control register (INT11IC)
Timer B1 interrupt control register (TB1IC)
SCL1,SDA1 interrupt control register (SCLDA1IC)
INT10 interrupt control register (INT10IC)
Timer B2 interrupt control register (TB2IC)
Key input interrupt 1 control register (KUP1IC)
INT0 interrupt control register (INT0IC)
PS20 interrupt control register (PS20IC)
INT1 interrupt control register (INT1IC)
PS21 interrupt control register (PS21IC)
INT2 interrupt control register (INT2IC)
PS22 interrupt control register (PS22IC)
027D16
027E16
027F16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-2 Location of peripheral unit control registers (1)
Rev.1.00 Jun 06, 2003 page 23 of 290