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M16C6K9 Datasheet, PDF (188/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |||
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M16C/6K9 Group
MULTI-MASTER I2C-BUS Interface
â¢Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. After each byte data is transmitted, the PIN bit changes from
â1â to â0â. At the same time, an I2C interrupt request signal occurs to the CPU. The PIN bit is set to â0â
synchronized with the falling edge of the last internal transmitting clock (including the ACK clock) and an
interrupt request signal occurs synchronized with the falling edge of the PIN bit. When the PIN bit is â0â, the
SCL is kept in the â0â state and clock generation is disabled. In the ACK clock enable mode, if WIT bit (bit 1
of I2C control register 1) is set to â1â, synchronized with the falling edge of last bit clock and ACK clock, PIN
bit becomes to â0â and I2C interrupt request is generated (Refer to the description on bit 1 of I2C control
register 1: the data reception completion interrupt enable bit). Fig.GC-9 shows the timing of I2C interrupt
request generation. The bit is read-only, the value should be â0â in writing.
The PIN bit is set to â0â in one of the following condition:
â¢Executing a write instruction to the I2C data shift register (address 032016, 033016, 031016).
â¢Executing a write instruction to the I2C clock control register (Address : 032416, 033416, 031416)
(only when WIT is â1â and internal WAIT flag is â1â)
â¢When the ES0 bit is â0â
â¢At reset
The PIN bit is set to â0â in one of the following condition:
â¢Immediately after the completion of 1-byte data transmission (including arbitration lost is detected)
â¢Immediately after the completion of 1-byte data reception
â¢In the slave reception mode, with ALS = â0â and immediately after the completion of slave address agreement
or general call address reception
â¢In the slave reception mode, with ALS = â1â and immediately after the completion of address data reception
â¢Bit 5: Bus busy flag (BB)
This bit indicates the in-use status the bus system. When this bit is set to â0â, bus system is not busy and a
START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of
master/slave. This flag is set to â1â by detecting the start condition, and is set to â0â by detecting the stop
condition. The condition of the detecting is set by the start/stop condition setting bits (SSC4âSSC0) of the
I2C start/stop condition control register (address 032516, 033516, 031516). When the ES0 bit (bit 3) of the I2C
control register (address 032316, 033316, 031316) is â0â or reset, the BB flag is set to â0â. For the writing
function to the BB flag, refer to the sections âSTART Condition Generating Methodâ and âSTOP Condition
Generating Methodâ described later.
â¢Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication. When this bit is â0â, the reception mode is
selected and the data from a transmitting device is received. When the bit is â1â, the transmission mode is
selected and address data and control data are output onto the SDA synchronized with the clock gener-
ated on the SCL. This bit can be set/reset by software or hardware. This bit is set to â1â by hardware in the
following condition:
In slave mode with ALS = â0â, if the AAS flag is set to â1â after the address data reception and the received
___
R/W bit is â1â.
This bit is set to â0â by hardware in one of the following conditions:
â¢When arbitration lost is detected.
â¢When a STOP condition is detected.
â¢When a start condition is prevented by the start condition duplication preventing function (Note).
â¢When a start condition is detected with MST = â0â.
â¢When ACK non-return is detected with MST = â0â.
â¢When ES0 = â0â.
â¢At reset
Rev.1.00 Jun 06, 2003 page 188 of 290
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