M16C6K9 Datasheet, PDF (47/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection
bits and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated
by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bits are located
in the interrupt control register of each interrupt. The interrupt enable flag (I flag) and the IPL are located in
the flag register (FLG).
Fig.DD-3 and DD-4 shows the memory map of the interrupt control registers.
The interrupt factors in the same vector share the same interrupt control register. Which factor to be used
depends on interrupt factor selection bit of interrupt event selection register i(address:035F16,035616,
to 035816, i = 0 to 3) setting. After setting the interrupt factor, the corresponding interrupt request bit must be
set to "0" before changing the interrupt.
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC2IC
SCLDA2IC/DM0IC
TB5IC/LRSTIC
TB4IC/S1RIC/S4IC
TB3IC/S1TIC
KUP0IC
ADIC
S2TIC/IBF0IC
S2RIC/IBF1IC
SiTIC/IICjIC(i=0,1)
(j=0,1)
TAiIC(i=0,2)
TAiIC/IBFjIC(i=3,4)
(j=2,3)
TB2IC/KUP1IC
Address
004116
004216
004316
004616
004716
004D16
004E16
004F16
005016
005116,005316
005116,005316
005516,005716
005816,005916
005816,005916
005C16
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
Nothing is assigned.
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Note 1: Can only be writing by “0” (Please do not write “1” to this bit)
Fig.DD-3 Interrupt control registers(1)
Rev.1.00 Jun 06, 2003 page 47 of 290