M16C6K9 Datasheet, PDF (128/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
S I/O3, 4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
When reset
SiC 036216, 036616
4016
Bit
symbol
SMi0
Bit name
Internal synchronous
clock selection bits
SMi1
SMi2 SOUTi output disable bit
SMi3 S I/Oi port selection bit
(Note 2)
Reserved bit
Description
RW
b1 b0
0 0 : Selecting f1
0 1 : Selecting f8
1 0 : Selecting f32
1 1 : Not to be used
0 : SOUTi output
1 : SOUTi output disable (high impedance)
0 : Input-output port
1 : SOUTi output, CLK function
Must be "0"
SMi5
SMi6
SMi7
Transfer direction
selection bit lect bitç
Synchronous clock
selection bit (Note 2)
SOUTi initial value
set bit
0 : LSB first
1 : MSB first
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/Oi control register (i = 3, 4).
Note 2: When SI/Oi port selection bit (i= 3, 4) is set to "0" as for I/O port, set the
synchronous clock selection bit to "1".
SI/Oi bit rate generator
b7
b0
Symbol
S3BRG
S4BRG
Address
036316
036716
When reset
Indeterminate
Indeterminate
Indeterminate
Assuming that set value = n, BRGi divides the count
source by n + 1
Values that can be set R W
0016 to FF16
SI/Oi transmission/reception register
b7
b0
Symbol
S3TRR
S4TRR
Address
036016
036416
When reset
Indeterminate
Indeterminate
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
RW
Fig.GA-29 S I/O3, 4 control registers
Rev.1.00 Jun 06, 2003 page 128 of 290