M16C6K9 Datasheet, PDF (102/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
When reset
03A016, 03A816
0016
Bit
symbol
Bit name
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
RW
SMD0 _{Serial I/O mode selection}
bits
SMD1
SMD2
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR ^{Internal/external clock}
selection bit
STPS Stop bit length selection
bit
0 : Internal clock
1 : External clock (Note 1)
Invalid
PRY Odd/even parity selection Invalid
bit
PRYE Parity enable bit
Invalid
SLEP Sleep selection bit
Must always be “0”
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
0 : Internal clock
1 : External clock (Note 1)
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note 1: Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
Bit
symbol
Bit name
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
RW
SMD0
SMD1
Serial I/O mode selection
bits
SMD2
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR ^{Internal/external clock}
selection bit
0 : Internal clock
Must always be "0"
1 : External clock (Note 1)
STPS Stop bit length selection _Invalid
bit
PRY Odd/even parity selection Invalid
bit
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE Parity enable bit
IOPOL ^{TxD, RxD I/O polarity}
switching bit
Invalid
0 : Not reverse
1 : Reverse
Usually set to “0”
0 : Parity disabled
1 : Parity enabled
0 : Not reverse
1 : Reverse
Usually set to “0”
Note 1: Set the corresponding port direction register to "0".
Fig.GA-5 Serial I/O-related registers (2)
Rev.1.00 Jun 06, 2003 page 102 of 290