M16C6K9 Datasheet, PDF (129/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
S I/O3, 4
Table.GA-9 Specifications of S I/O3, 4
Item
Transfer data format
Transfer clock
Conditions for
transmission/
reception start
Interrupt request
generation timing
Specifications
• Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1),
f8/2(ni+1), f32/2(ni+1) (Note 1)
• With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2)
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 of 036216, 036616).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 of 036216, 036616).
- SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1.
- S I/Oi port select bit (bit 3 of 036216, 036616) = 1.
- Select the transfer direction (use bit 5 of 036216, 036616)
- Write transfer data to SI/Oi transmission/reception register(036016, 036416)
• To use S I/Oi interrupts, the following requirements must be met:
- S I/Oi interrupt request bit (bit 3 of 004916, 004816) = 0.
• At the rising edge of the last transfer clock (Note3)
Select function
Precaution
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be
selected.
• The SOUTi default value setting function
If the transfer clock is selected to external clock, the output level of SOUTi pin
can be selected when it is not in transferring please refer to Fig.GA-30.
• The SI/Oi (i=3,4) is different from UART0 to 2 that the register and buffer can not
be separated, so don't write the next transfer data to the transmission/reception
register(036016, 036416) during transferring.
• If the transfer clock is selected to internal clock, at the end of transferring, the
SOUTi holds the last data during the last 1/2 transfer clock, and then to high impedance.
If the transmission/reception register(036016, 036416) is written during the period,
the SOUTi becomes the high impedance right the writing ,the data hold time will be
shortened.
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4).
Note 2: With the external clock selected:
• Please write to the SI/Oi transmission/reception register(036016, 036416) under the status that the
CLKi pin is input to "H" level. Also please write to the bit 7(SOUTi default value setting bit) under
the status that the CLKi pin is input to "H" level.
• The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
Rev.1.00 Jun 06, 2003 page 129 of 290