M16C6K9 Datasheet, PDF (122/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable
“1”
bit(TE)
“0”
Transmit buffer
“1”
empty flag(TI)
“0”
TxD2
RxD2
Signal conductor level
(Note1)
Transmit register
“1”
empty flag (TXEPT)
“0”
Transmit interrupt ^{“1”}
request bit (IR)
“0”
Data is set in UART2 transmit buffer register Note1
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P _SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A "L" level returns from TxD2 due to the
occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P _SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P
The level is detected by
the interrupt routine
SP
The level is detected by
the interrupt routine
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note 1. According to the above timing, the transmission is started by the timing of BRG overflow after writing to the transmit buffer.
Tc
Transfer clock
Receive enable
“1”
bit(RE)
“0”
RxD2
Start
bit
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2
Signal conductor level
(Note 2)
Receive complete “1”
flag (RI)
“0”
Receive interrupt
“1”
request bit (IR)
“0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A "L" level returns from TxD2 due to the
occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Read to receive buffer
Read to receive buffer
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note 2. The waveforms are the same because TxD2 and RxD2 are connected.
Fig.GA-22 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Rev.1.00 Jun 06, 2003 page 122 of 290