M16C6K9 Datasheet, PDF (70/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher
right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the
operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte
(8-bit) data transfer can be performed at high speed. Fig.EC-1 shows the block diagram of the DMAC.
Table.EC-1 shows the DMAC specifications. Fig.EC-2 to EC-4 show the registers used by the DMAC.
Address bus
DMA0 transfer counter reload register TCR0 (16)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816)
DMA1 transfer counter TCR1 (16)
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 forward address pointer (20) (Note)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Fig.EC-1 Block diagram of DMAC
Note: Pointer is incremented by a DMA request.
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt
priority level. The DMA transfer doesn't affect any interrupts neither.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer
cycle, there can be instances in which the number of transfer requests doesn't agree with the number of
transfers. For details, see the description of the DMA request bit.
Rev.1.00 Jun 06, 2003 page 70 of 290