M16C6K9 Datasheet, PDF (55/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
_______ ________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Fig.DD-9 Hardware interrupts priorities
Priority level of each interrupt
INT1/PS21
Timer B2/Key input interrupt 1
Timer B0/INT11/SCL0,SDA0
Timer A3/IBF2
Level 0 (initial value)
Timer A1/INT7/SIO3
UART1 reception/SCL1,SDA1/INT10
UART0 reception/SCL0,SDA0/INT11
UART2 reception/ IBF1
INT2/PS22
INT0/PS20
Timer B1/INT10/SCL1,SDA1
Timer A4/IBF3
Timer A2
Timer A0
UART1 transmission/ I²C1
UART0 transmission/ I²C0
A-D conversion
DMA1/INT7
Bus collision detection/INT4
SIO4/INT6
Timer B4/ UART1 reception/ SIO4
INT3
SCL2, SDA2/ DMA0
UART2 transmission/IBF0
Key input interrupt 0
INT8
SIO3/INT5
Timer B3/ UART1 transmission
INT9
Timer B5/ LRESET
I²C2
(Note 1)
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
NMI
Reset
Note 1: I²C exist in M306K9FCLRP
Fig.DD-10 Interrupt priority judgement circuit
High
Priority of peripheral I/O interrupts
(if priority levels are same)
Low
To interrupt request level judgment output
clock generation circuit (Fig. WA-3)
Interrupt
request
accepted
Rev.1.00 Jun 06, 2003 page 55 of 290