M16C6K9 Datasheet, PDF (193/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
•The address reception in STOP mode /WAIT mode
It is possible for I²C-BUS interface to receive address data even in STOP mode or in WAIT mode. However
the I²C system clock VIIC should be supplied. Table.GC-6 shows the setting list.
Table.GC-6 Clock setting to the I²C system in different operation mode.
Mode
STOP mode
WAIT mode
The setting content
The external clock is selected as the I²C system clock ( ICK1 = 1, ICK0 = 1) and
the external I²C clock is supplied by ICCK.
The external clock is selected as the I²C system clock ( ICK1 = 1, ICK0 = 1) and
the external I²C clock is supplied by ICCK.
Select the peripheral function clock stop bit CMO2 (bit 2 of the system clock
control register 0, address : 000616) to the state of not stopping f1,f8,f32
Low power
consumption mode
(CMO2 = 0) when in WAIT mode, and then execute the WAIT command.
The external clock is selected as the I²C system clock ( ICK1 = 1, ICK0 = 1) and
the external I²C clock is supplied by ICCK.
When in reception mode, ACK bit = "1" WIT bit = "0"
SCL
SDA
ACKBIT
PIN flag
Internal WAIT flag
I²C interrupt request signal
The writing signal of I²C
data shift register
7 clock
7 bit
8 clock
8 bit
ACK
clock
ACK bit
1 clock
1 bit
When in reception mode, ACK bit = "1" WIT bit = "1"
SCL
7 clock
8 clock
SDA
7 bit
8 bit
ACKBIT
PIN flag
Internal WAIT flag
I²C interrupt request signal
➀
The writing signal of I²C
data shift register
The writing signal of I²C
clock control register
ACK
clock
1 bit
➁
Note. Do not write to I²C clock control register except bit ACKBIT.
Fig.GC-10 The timing of the interrupt generation at the completion of data reception
Rev.1.00 Jun 06, 2003 page 193 of 290