M16C6K9 Datasheet, PDF (51/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the execu-
tion of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an
interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor
temporarily suspends the instruction being executed, and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63,
is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the procession of interrupt sequence the processor executes instructions from the first address of the
interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruc-
tion within the interrupt routine has been executed. This time comprises the period from the occurrence of
an interrupt to the completion of the instruction under execution at that moment (a) and the time required for
executing the interrupt sequence (b). Fig.DD-5 shows the interrupt response time.
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Fig.DD-5 Interrupt response time
Time
Instruction in
interrupt routine
Rev.1.00 Jun 06, 2003 page 51 of 290