M16C6K9 Datasheet, PDF (187/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
I²C Status Register
The I²C status register (address 032816, 033816, 031816) controls the I²C-BUS interface status. The low-
order 6 bits are read-only if it is used for status check. The high-order 2 bits can be both read and written.
Regarding to the function of writing to the low-order 6 bits, refer to the method of start condition/stop condi-
tion generation described later.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK
is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”.
Except in the ACK mode, the last bit value of received data is input. The bit will be “0” by executing a
write instruction to the I²C data shift register (address 032016, 033016, 031016).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call* whose address data is all “0” is received in
the slave mode. By a general call of the master device, every slave device receives control data after the
general call. The AD0 bit is set to “0” by detecting the STOP condition, START condition, or ES0 is“0”, or
reset.
*General call: The master transmits the general call address “0016” to all slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the ALS bit is “0”.
1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the
following conditions:
• The address data, which following the start conduction, is same with upper bits data of I²C address
register(Address 032216, 033216, 031216)
• A general call is received.
2)In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the
following condition:
• When the address data is compared with the I²C address register (8 bits consisting of slave address and
RBW bit), the first bytes agree.
3)This bit is set to “0” by executing a write instruction to the I²C data shift register (address 032016, 033016,
031016) when ES0 is set to “1”. The bit is also set to “0” when ES0 is set to “0” or when reset.
•Bit 3: Arbitration lost* detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have
been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”. Immediately after transmis-
sion of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be
detected only in the master transmission mode. When arbitration is lost during slave address transmission,
the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the
agreement between its own slave address and address data transmitted by another master device. The bit is
cleared to “0” if writing to I²C data shift register (address 032016, 033016, 031016) when ES0 is “1”.
The bit is also cleared to “0” when ES0 is set to “0” or when reset.
*Arbitration lost: The status in which communication as a master is disabled.
Rev.1.00 Jun 06, 2003 page 187 of 290