M16C6K9 Datasheet, PDF (178/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
MULTI-MASTER I²C-BUS Interface
The multi-master I²C-BUS interface is a serial communication circuit based on Philips I²C-BUS data transfer
format. 3 independent channels, with both arbitration lost detection and a synchronous functions, are built in
for the multi-master serial communication. Fig.GC-1 shows a block diagram of the multi-master I²C-BUS
interface and Table.GC-1 lists the multi-master I²C-BUS interface functions. The multi-master I²C-BUS in-
terface consists of the I²C address register, the I²C data shift register, the I²C clock control register, the I²C
control register 1, I²C control register 2, the I²C status register, the I²C start/stop condition control register
and other control circuits.
Note 1: 2 independent channels exist in M306K9F8LRP.
Table.GC-1 Multi-master I²C-BUS interface functions
Item
Function
Based on Philips I²C-BUS standard:
10-bit addressing format
Format
7-bit addressing format
High-speed clock mode
Standard clock mode
Based on Philips I²C-BUS standard:
Master transmission
Communication mode
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1kHz to 400kHz (at VIIC = 4MHz)
*VIIC=I²C system clock
Rev.1.00 Jun 06, 2003 page 178 of 290