M16C6K9 Datasheet, PDF (167/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial Interrupt Output
Serial Interrupt Output
The serial interrupt output is the circuit that outputs the interrupt request to the host with serial interrupt
data format.
Tab.SI-1 shows the specification of serial interrupt output.
Table.SI-1 Specifications of serial interrupt output
Item
The factors of serial interrupt
The number of frame
Operation clock
Clock restart
Clock stop inhibition
OBF sync enable
Specification
The numbers of serial interrupt requests (numbers of channels) that can output simul-
taneously are 5 factors. Each interrupt factor of each channel is explained as follows.
• Channel 0
➀ By setting “1” to IRQi request bit (bit 5, 6 i=1,12) of IRQ request register 0, the interrupt
request can be generated.
➁ Synchronized with OBF00 and OBF01 that are the host bus interface internal signals,
the serial interrupt request can be generated.
• Channel 1-3
➀ By setting “1” to IRQ request bit (bit 5) of IRQ request register 1-3, the interrupt
request can be generated.
➁ Synchronized with OBF1-3 that are the host bus interface internal signals, the serial
interrupt request can be generated.
• Channel 4
By setting “1” to IRQ request bit (bit 5) of IRQ request register 4, the interrupt request can be
generated.
• Channel 0
➀ Setting the IRQ1 request bit (bit 5) of IRQ request register0 to “1” or detecting
OBF00, which is the host bus interface internal signal, selects Frame 1.
➁ Setting the IRQ12 request bit (bit 6) of IRQ request register0 to “1” or detecting
OBF01, which is the host bus interface internal signal, selects Frame 12.
• Channel 1-4
Selecting the frame select bit (bit 0-4) of IRQ request register1-4 selects Frame 1-15
or extend Frame 0-10.
The operation synchronized with LCLK (Max. 33MHz). (Note)
Setting the clock restart enable bit (bit 6) of serial interrupt control register0 to “1”
requests the clock restart if the clock has stopped or slowed down in serial interrupt
output.
Setting the clock stop inhibition bit (bit 5) of serial interrupt control register0 to “1”
requests the inhibition of clock stop if the clock tends to stop or slow down in serial
interrupt output.
Setting the OBF00, OBF01, OBF1-3 sync enable bit (bit 0-4) of serial interrupt con-
trol register0 to “1” enables the OBF synchronization.
Note: To enable LCLK, it is necessary to enable the LPC bus interface function.
Rev.1.00 Jun 06, 2003 page 167 of 290