M16C6K9 Datasheet, PDF (169/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial Interrupt Output
(1) Register explanation
Fig.SI-2 shows the configuration of IRQ request register0, Fig.SI-3 shows the configuration of
IRQ request register1-4, Fig.SI-4, SI-5 show the configurations of serial interrupt control regis-
ter0,1 respectively.
q IRQ request register0 IRQR0
The serial interrupt request of Channel 0 is set by software.
•IRQ1 request bit IR0
Setting the bit to “1” generates the serial interrupt request (Frame 1).
By setting the OBF00 sync enable bit (bit 0) of the serial interrupt control register0 to “1”, the value
of IR0 is the same as that of OBF00, which is the host bus interface internal signal. When the
internal signal OBF00 is “1”, the serial interrupt is generated.
IR0 is cleared to “0” by writing “0” in software.
IR0 can not be cleared to “0” by software when the internal signal OBF00 is “1” if OBF00 sync
enable bit is set to “1”.
•IRQ12 request bit IR1
Setting the bit to “1” generates the serial interrupt request (Frame 12).
By setting the OBF01 sync enable bit (bit 1) of the serial interrupt control register0 to “1”, the value
of IR1 is the same with that of OBF01, which is the host bus interface internal signal. When the
internal signal OBF01 is “1”, the serial interrupt is generated.
IR1 is cleared to “0” by writing “0” in software.
IR1 can not be cleared to “0” by software when the internal signal OBF01 is “1” if OBF01 sync
enable bit is set to “1”.
IRQ request register0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol: IRQR0 Address: 02B216 When reset: 0016
Bit symbol
Bit name
Nothing is assigned.
Meaningless in writing, “0” in reading.
Function
IR0 IRQ1 request bit
IR1 IRQ12 request bit
0: No IRQ1 request
1: IRQ1 request
0: No IRQ12 request
1: IRQ12 request
Nothing is assigned.
Meaningless in writing, “0” in reading.
RW
Fig.SI-2 Configuration of IRQ request register0
Rev.1.00 Jun 06, 2003 page 169 of 290