M16C6K9 Datasheet, PDF (73/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
DMAC
DMA1 request factor selection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BA16
When reset
0016
Bit symbol
DSEL0
Bit name
DMA request factor
selection bits
DSEL1
DSEL2
DSEL3
Function
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
/serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit (DMS=0)
/IBF0(DMS=1)
1 0 1 1 : UART0 receive (DMS=0)
/IBF1(DMS=1)
1 1 0 0 : UART2 transmit(DMS=0)
/IBF2(DMS=1)
1 1 0 1 : UART2 receive(DMS=0)
/IBF3(DMS=1)
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
DMS
DSR
DMA request factor
expansion bit
Software DMA
request bit
0 : Normal
1 : Expanded factor
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X002
RW
Bit symbol
Bit name
Function
RW
DMBIT
DMASL
Transfer unit bit select bit
Repeat transfer mode
select bit
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1) ^{0 : DMA not requested}
1 : DMA requested
(Note 2)
DMAE
DSD
DMA enable bit
Source address direction
select bit (Note 3)
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) _{1 : Forward}
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit to "0".
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Fig.EC-3 DMAC register (2)
Rev.1.00 Jun 06, 2003 page 73 of 290