M16C6K9 Datasheet, PDF (49/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag
to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0”
after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bits in the interrupt control register.
When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is en-
abled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt
priority level to “0” disables the interrupt.
Table.DD-3 shows the settings of interrupt priority levels and Table.DD-4 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > processor interrupt priority level (IPL)
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bits, and the IPL are
independent, and they are not affected each other.
Table.DD-3 Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
b2 b1 b0
000
Level 0 (interrupt disabled)
001
Level 1
010
Level 2
011
100
Level 3
Level 4
101
Level 5
110
Level 6
111
Level 7
Priority
order
Low
High
Table.DD-4 Interrupt levels enabled according
to the contents of the IPL
IPL
IPL2 IPL1 IPL0
000
001
010
011
100
101
110
111
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Rev.1.00 Jun 06, 2003 page 49 of 290