M16C6K9 Datasheet, PDF (131/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5
at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D con-
version only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table.JA-1 shows the performance of the A-D converter. Fig.JA-1 shows the block diagram of the A-D
converter, and Fig.JA-2 and JA-3 show the A-D converter-related registers.
Table.JA-1 Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage
0V to AVCC (VCC)
Operating clockφAD (Note1) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
• 8-bit resolution
±2LSB
• 10-bit resolution
±6LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin
• Without sample and hold function
8-bit resolution : 49 φAD cycles
10-bit resolution : 59 φAD cycles
• With sample and hold function
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
Note 1: The frequency φAD should be set to 250kHz min and 8MHz max.
Without sample and hold function,set the φAD frequency to 250kHz min.
With the sample and hold fucntion, set the φAD frequency to 1MHz min.
Rev.1.00 Jun 06, 2003 page 131 of 290